matrix
The matrix control circuitry interprets the matrix control bitstream from the Digital Output Combiner boardand generates the appropriate control signals for the matrix crosspoint chips.The Digital Output Combiner board provides matrix control information in the form of a serial bitstream onsignals MTX_DATA, MTX_CLK, and MTX_SB. Video reference timing is also provided on MTX_VT(vertical trigger). The serial bitstream is decoded by U24, U26, U28, U29, U31, and various support gates.U25 pins 1,2, and 3 gate the incoming clock signal such that MTX_DATA is shifted into U24 pin 1 onlywhen MTX_STB is active (high) and MTX_CLK pulses are present. This data is presented in parallelformat on the output of U24. Each set of 8 bits (one byte) represents the input data for one of the 16 outputscontrolled by the Digital Video Output Combiner generated bitstream. Each of the three 48×16 DigitalCrosspoint boards is assigned a slot ID (MTX_ID_1:0) of 0, 1, or 2. The input data in the bitstreamcontains encoded “slot” information in the two upper bits of each byte (U24 pins 12 and 13). If theembedded slot code matches the ID code, the input contained in the bitstream is intended for the 48×16Digital Crosspoint board. XOR gates U30 pins 4, 5, 6, 8, 9, and 10 are used to compare the embedded slotcode with the matrix ID code. When the code matches, U31 is enabled (U31 pins 4 and 5). The remainingbits of each byte contain additional input information. The lower four bits (U24 pins 3, 4, 5, and 6) containthe modulo-16 input number. The remaining two bits (U24 pins 10 and 11) contain encoded informationrepresenting with group of 16 inputs is selected. A code of 0 indicates that the input is active in the firstgroup of 16 inputs (1-16). A code of 1 represents the inputs 17-32, and a code of 2 represents inputs 33-48.A code of 3 is reserved for the off state, where no input is active on the designated card. The crosspointchips are eight inputs by eight outputs, requiring that the input information be expressed in modulo-8format. In addition, each crosspoint has a tri-state input bit (T0-T5) that are used to force an output into thetri-state condition. Decoder U31 generates the tri-state control inputs based on the input number, the groupcode, and the ID. Only one of T0-T5 are active at any given time. If the ID doesn’t match, none of T0-T5are active for this output.U29 is a modulo-8 counter that keeps track of the bit position currently being shifted into the controlcircuit. U26 decodes the bit count and provides output signals during certain bit times. Counter U28 keepstrack of the output currently being addressed. The bitstream contains output 16 data followed by output 15,output 14, and etc. down to output 1. U28 is initialized to 0 whenever MTX_STB is inactive, and countsdown during cycle 2 of each control byte (when U26 pin 13 is active). During cycle 7 of each control byte,U26 pin 7 becomes active, causing U27 to change states for one clock cycle. This single cycle pulse is usedto gate the MTX_CLK signal (inverted by U30 pins 11, 12, and 13; gated by U25 pins 11, 12, 13) toprovide the LOAD signal for the crosspoint ICs. When LOAD occurs, the current input data (T0-T5 andIA0-2) is latched into the crosspoint addressed by the output represented by OA0-3.